In the field of semiconductor device manufacturing, active semiconductor devices such as, for example, transistors are normally manufactured or fabricated by front end of line (FEOL) technologies. A transistor may include, for example, a field-effect-transistor (FET) such as a complementary metal-oxide-semiconductor (CMOS) FET. Among FET transistors may be a p-type doped FET (PFET) or an n-type doped FET (NFET). Different types of FET transistors may be formed or manufactured on a common substrate of semiconductor chip or a common semiconductor structure.
In order to improve device performance such as operational speed by enhancing carrier mobility in the channel of a FET, following forming the gate structure of the FET, stresses are normally induced into the channel region of the FET through, for example, applying stress liners. A compressive stress liner is normally applied to a PFET transistor and a tensile stress liner applied to an NFET transistor due to different types of carriers. Both stress liners may be formed by following a conventional dual stress liner (DSL) process, or more recently a self-aligned dual stress liner process (SADSL). Other techniques for engineering strain in the channel of a FET may include, for example, embedding silicon germanium (SiGe) in the source/drain regions of a PFET transistor so as to more effectively apply stress towards the channel of the PFET transistor.
With the continued pursuing for high-performance semiconductor devices, there is a need to further improve the engineering of strain in the channel region of field-effect-transistors. This may include, for example, improving the effectiveness of stress liners and in some instances even in the absence of such stress liners.